This application relates to a high speed data transmission system and, specifically, to a method and apparatus for improved data encoding in a multiplexed, high speed data transmission.
Many conventional data transmission systems monitor the synchronization of received data frames to verify that the received data is in synchronization with a xe2x80x9csuperframexe2x80x9d that contains a plurality of multibit xe2x80x9cframesxe2x80x9d. The synchronization monitor may use a method which is too ready to declare loss of synchronization, and is also less ready than is absolutely necessary to declare reestablishment of synchronization (the loss of synchronization forces a total loss of data traffic). A data transmission system that refuses to detect loss of synchronization until the worst possible operating conditions will work best with error correction.
Many conventional data transmission systems use some type of error correction (EC) encoding to send data from transmitter to a receiver. For example, ITU Recommendation G.742, which governs E1 and E2 data transmissions, specifies that each multibit xe2x80x9cframexe2x80x9d of E2 data contains one xe2x80x9cjustification control flagxe2x80x9d formed of three redundant justification control bits (also called xe2x80x9cstuff bitsxe2x80x9d) per each of the four multiplexed E1 xe2x80x9ctributaries.xe2x80x9d These justification bits are used by the data transmission system to control the justification of received data. ITU Recommendation G.742 is herein incorporated by reference.
As is well-known in the art, three justification control bits per justification control flag allows one error in one justification control bit to be corrected. In this conventional method (majority decision), errors in two or more of the justification control bits cause the justification control flag value to be incorrect.
One type of error in the multibit E2 frame, an error in the justification control flag for an E1 tributary, causes that E1 tributary to experience a synchronization loss or xe2x80x9cpattern slip.xe2x80x9d
When the frame is modified (by adding two-bit EC to the frame) so that the error threshold begins at three errors per frame, the uncorrected E2 frame bit error rate (xe2x80x9cE2 BERxe2x80x9d) level at which pattern slips occur changes very little, although the E1 tributary bit error rate (xe2x80x9cE1 BERxe2x80x9d) is actually greatly improved a that E2 BER level by the two-bit EC. The rate of pattern slips is therefore greatly increased with respect to the E1 BER.
A way of improving the EC of the justification control flag alone, rather than pay the cost of improving the EC of the frame as a whole, and an improved algorithm for superframe synchronization, which together greatly improve the synchronization loss level of the system with only a very slight decrease in data information efficiency, are needed.
The present invention provides a method and apparatus for detecting loss of synchronization in superframe data and a method and apparatus for detecting resynchronization of a superframe. In addition, the number of justification bits is increased to increase the reliability of the justification flag value without having to add extra error correction circuitry. In a first preferred embodiment of the present invention, a justification flag includes seven justification bits instead of three. In a second preferred embodiment of the present invention a justification flag includes five justification bits.
Another preferred embodiment of the present invention allows backward compatibility between systems having different numbers of justification bits. In order to maintain field compatibility with earlier three bit justification systems, a dedicated bit in the frame, which has a fixed value of xe2x80x9c1xe2x80x9d in the old system is altered to a value of xe2x80x9c0,xe2x80x9d as a backwards compatibility flag. Newer systems will detect the xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d at this flag location and activate the proper circuitry to affect the old or new justification method. In this way, a new system can be interconnected with an older system and still function. In order to insure correct recovery of this crucial flag bit in the newer system even under high error rate conditions, the value is sampled for many consecutive frames and only updated if all bits are identical and different from the stored value. A preferred embodiment samples eight consecutive frames.
Thus, the present invention performs more efficient detection of synch loss and detection of resynch. The present invention also incorporates an improved justification method, which, in a preferred embodiment of the present invention, can be backwards compatible with older systems.
In accordance with the purpose of the invention, as embodied and broadly described herein, the invention relates to a method of determining a loss of synchronization in a plurality of frames in a superframe, comprising the steps, performed by a high speed data receiver, of: receiving the plurality of frames, each frame having a respective bit of a plurality of superframe synchronization bits; and comparing the received superframe synchronization bits to a predefined superframe synchronization pattern; determining, if there are at least six errors in the received superframe synchronization bits, that the superframe has lost synchronization.
In further accordance with the purpose of this invention, as embodied and broadly described herein, the invention relates to a method of regaining synchronization of a plurality of frames in a superframe after synchronization has been lost, comprising the steps, performed by a high speed data receiver, of: receiving a plurality of frames, each frame having a respective bit of a plurality of superframe synchronization bits; and comparing the received superframe synchronization bits to a predefined superframe synchronization pattern; and determining, if the received superframe synchronization bits are equal to at least a first number of consecutive bits of the predefined superframe synchronization pattern, that the superframe has regained synchronization.
In further accordance with the purpose of this invention, as embodied and broadly described herein, the invention relates to method of determining whether a stuff opportunity in a frame contains valid data, comprising the steps, performed by a high speed data receiver, of: receiving a high speed data stream, including seven justification control bits; determining a majority value of the justification control bits; and determining, if the majority value of the justification control bits is xe2x80x9c1xe2x80x9d that a stuff opportunity contains valid data.
A fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.